library ieee;
use ieee.std_logic_1164.all;

-- This arbitrary state machine is probably not very useful in reality, but demonstrates 

entity forward_test is
    port (clock               : in  std_logic;
	      out_clock			  : out std_logic;
          reset               : in  std_logic;
          FWD_to_RCV0_LENGTH_ACK_out, FWD_to_RCV1_LENGTH_ACK_out, FWD_to_RCV2_LENGTH_ACK_out, FWD_to_RCV3_LENGTH_ACK_out 	: OUT STD_LOGIC;
	      FWD_to_RCV0_FRAME_ACK_out, FWD_to_RCV1_FRAME_ACK_out, FWD_to_RCV2_FRAME_ACK_out, FWD_to_RCV3_FRAME_ACK_out		: OUT STD_LOGIC;
	      FWD_to_TBL_ACK_out																					: OUT STD_LOGIC;
		  FWD_to_TBL_desAddress_out																				: OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	      FWD_to_TBL_srcPort_out																				: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	      FWD_to_TBL_srcAddress_out																				: OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	      FWD_to_XMT0_DATA_out, FWD_to_XMT1_DATA_out, FWD_to_XMT2_DATA_out, FWD_to_XMT3_DATA_out							: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	      FWD_to_XMT0_ACK_out, FWD_to_XMT1_ACK_out, FWD_to_XMT2_ACK_out, FWD_to_XMT3_ACK_out								: OUT STD_LOGIC;
	      FWD_to_XMT0_DONE_out, FWD_to_XMT1_DONE_out, FWD_to_XMT2_DONE_out, FWD_to_XMT3_DONE_out							: OUT STD_LOGIC;
	      FWD_to_XMT0_LENGTH_out, FWD_to_XMT1_LENGTH_out, FWD_to_XMT2_LENGTH_out, FWD_to_XMT3_LENGTH_out					: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
	      RCV0_to_FWD_DATA_out, RCV1_to_FWD_DATA_out, RCV2_to_FWD_DATA_out, RCV3_to_FWD_DATA_out                            : out std_logic_vector(7 downto 0);
	      RCV0_to_FWD_LENGTH_out, RCV1_to_FWD_LENGTH_out, RCV2_to_FWD_LENGTH_out, RCV3_to_FWD_LENGTH_out                    : out std_logic_vector(11 downto 0);
	      RCV0_to_FWD_FRAMEAVAILABLE_out, RCV1_to_FWD_FRAMEAVAILABLE_out, RCV2_to_FWD_FRAMEAVAILABLE_out, RCV3_to_FWD_FRAMEAVAILABLE_out : out std_logic; 
	      TBL_to_FWD_ACK_out, TBL_to_FWD_Valid_out																					: out std_logic;
          TBL_to_FWD_Port_out : out std_logic_vector(2 downto 0);
	      testsrcAddress0Validout, testsrcAddress1Validout, testsrcAddress2Validout, testsrcAddress3Validout : OUT STD_LOGIC;
	      testdesAddress0Validout, testdesAddress1Validout, testdesAddress2Validout, testdesAddress3Validout : OUT STD_LOGIC;
          debug_portReady : OUT STD_LOGIC;																							   
          port_err, data_err, len_err, all_frames_through,pass                                                                                     : out std_logic;
          len_out0, len_out1, len_out2, len_out3 : out std_logic_vector(10 downto 0);
          portChoice : out std_logic_vector(1 downto 0);
          OMX_to_ARB_Done : out std_logic;
          num_frames_through : out std_logic_vector(10 downto 0);
          seed : in std_logic_vector(5 downto 0);
          num_frames: in std_logic_vector(7 downto 0);
          random_lengths : in std_logic
	      );
end forward_test;

architecture behavior of forward_test is

signal RCV0_to_FWD_DATA, RCV1_to_FWD_DATA, RCV2_to_FWD_DATA, RCV3_to_FWD_DATA											: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal RCV0_to_FWD_LENGTH, RCV1_to_FWD_LENGTH, RCV2_to_FWD_LENGTH, RCV3_to_FWD_LENGTH									: STD_LOGIC_VECTOR(11 DOWNTO 0);
signal RCV0_to_FWD_FRAMEAVAILABLE, RCV1_to_FWD_FRAMEAVAILABLE, RCV2_to_FWD_FRAMEAVAILABLE, RCV3_to_FWD_FRAMEAVAILABLE	: STD_LOGIC;
signal FWD_to_RCV0_LENGTH_ACK, FWD_to_RCV1_LENGTH_ACK, FWD_to_RCV2_LENGTH_ACK, FWD_to_RCV3_LENGTH_ACK: std_logic; --, FWD_to_RCV2_LENGTH_ACK, FWD_to_RCV3_LENGTH_ACK  
signal FWD_to_RCV0_FRAME_ACK, FWD_to_RCV1_FRAME_ACK, FWD_to_RCV2_FRAME_ACK, FWD_to_RCV3_FRAME_ACK : std_logic; --FWD_to_RCV2_FRAME_ACK, FWD_to_RCV3_FRAME_ACK : std_logic;

signal TBL_to_FWD_ACK, TBL_to_FWD_Valid																					: STD_LOGIC;
signal TBL_to_FWD_Port																									: STD_LOGIC_VECTOR(2 DOWNTO 0);
signal FWD_to_TBL_ACK																									: STD_LOGIC;
signal FWD_to_TBL_desAddress																							: STD_LOGIC_VECTOR(47 DOWNTO 0);
signal FWD_to_TBL_srcPort																								: STD_LOGIC_VECTOR(1 DOWNTO 0);
signal FWD_to_TBL_srcAddress																							: STD_LOGIC_VECTOR(47 DOWNTO 0);
	     
signal XMT0_to_FWD_spaceavailable, XMT1_to_FWD_spaceavailable, XMT2_to_FWD_spaceavailable, XMT3_to_FWD_spaceavailable	: STD_LOGIC_VECTOR(10 DOWNTO 0);
signal XMT0_to_FWD_ACK, XMT1_to_FWD_ACK, XMT2_to_FWD_ACK, XMT3_to_FWD_ACK												: STD_LOGIC;
    
signal FWD_to_XMT0_DATA, FWD_to_XMT1_DATA, FWD_to_XMT2_DATA, FWD_to_XMT3_DATA							: std_logic_vector(7 downto 0); 
signal FWD_to_XMT0_ACK, FWD_to_XMT1_ACK, FWD_to_XMT2_ACK, FWD_to_XMT3_ACK								: std_logic;
signal FWD_to_XMT0_DONE, FWD_to_XMT1_DONE, FWD_to_XMT2_DONE, FWD_to_XMT3_DONE							: std_logic;
signal FWD_to_XMT0_LENGTH, FWD_to_XMT1_LENGTH, FWD_to_XMT2_LENGTH, FWD_to_XMT3_LENGTH					: std_logic_vector(11 downto 0);
    
signal en_0,en_1,en_2			                                                                                        : std_logic := '0';
signal q																												: std_logic_vector(62 downto 0);
signal gen_0,gen_1,gen_2 : std_logic_vector(63 downto 0) := (63 downto 0 =>'0'); 

signal packet_size_comparator_out0, packet_size_comparator_out1, packet_size_comparator_out2, packet_size_comparator_out3 : std_logic;
signal packetType0, packetType1, packetType2, packetType3 :std_logic;

signal data_err0, data_err1, data_err2, data_err3     : std_logic;
signal port_err0, port_err1, port_err2, port_err3     : std_logic;
signal len_err0, len_err1, len_err2, len_err3         : std_logic;
signal data_err_int, port_err_int, len_err_int        : std_logic;

signal port_ever, data_ever, len_ever : std_logic := '0';

signal frame_count, frame_count0, frame_count1, frame_count2, frame_count3, frame_count01, frame_count23 : std_logic_vector(10 downto 0);
signal frame_out_count, frame_out_count0, frame_out_count1, frame_out_count2, frame_out_count3, frame_out_count01, frame_out_count23 : std_logic_vector(10 downto 0); 

signal arbiter_debug_portReady : STD_LOGIC;

signal IPv4_frame_count_out0, VLAN_frame_count_out0, IPv4_frame_count_out1, VLAN_frame_count_out1, IPv4_frame_count_out2, VLAN_frame_count_out2, IPv4_frame_count_out3, VLAN_frame_count_out3 	:	STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL pass_data_out0, pass_data_out1, pass_data_out2, pass_data_out3 : STD_LOGIC;
SIGNAL count_out0, count_out1, count_out2, count_out3 :  STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL srcAddress0Validout, srcAddress1Validout, srcAddress2Validout, srcAddress3Validout :  STD_LOGIC;
SIGNAL desAddress0Validout, desAddress1Validout, desAddress2Validout, desAddress3Validout :  STD_LOGIC;
SIGNAL sendingsrcAddress0out, sendingdesAddress0out, sendingsrcAddress1out, sendingdesAddress1out, sendingsrcAddress2out, sendingdesAddress2out, sendingsrcAddress3out, sendingdesAddress3out :  STD_LOGIC;


--SIGNAL portChoiceout :  STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL portReadyout  :  STD_LOGIC;
--SIGNAL OMX_to_ARB_Done_out :  STD_LOGIC;

COMPONENT Test_Forwarding_Engine IS

    PORT(
       
       -- Legit pins
       clr : IN STD_LOGIC;
       clk : IN STD_LOGIC;
       
       -- ForwardingBuffer.vhd
       data_available0, data_available1, data_available2, data_available3 : IN STD_LOGIC;
--       pass_data0, pass_data1, pass_data2, pass_data3 : IN STD_LOGIC;
       pass_data_out0, pass_data_out1, pass_data_out2, pass_data_out3 : OUT STD_LOGIC;
       IN_RCV0_to_FWD_DATA, IN_RCV1_to_FWD_DATA, IN_RCV2_to_FWD_DATA, IN_RCV3_to_FWD_DATA	: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	   IN_RCV0_to_FWD_LENGTH, IN_RCV1_to_FWD_LENGTH, IN_RCV2_to_FWD_LENGTH, IN_RCV3_to_FWD_LENGTH  	  : IN STD_LOGIC_VECTOR(11 DOWNTO 0); --MSB is valid bit
       OUT_FWD_to_RCV0_LENGTH_ACK, OUT_FWD_to_RCV1_LENGTH_ACK, OUT_FWD_to_RCV2_LENGTH_ACK, OUT_FWD_to_RCV3_LENGTH_ACK  : OUT STD_LOGIC;
	   OUT_FWD_to_RCV0_FRAME_ACK, OUT_FWD_to_RCV1_FRAME_ACK, OUT_FWD_to_RCV2_FRAME_ACK, OUT_FWD_to_RCV3_FRAME_ACK	  : OUT STD_LOGIC;
--       data_out0, data_out1, data_out2, data_out3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       count_out0, count_out1, count_out2, count_out3 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
       srcAddress0Validout, srcAddress1Validout, srcAddress2Validout, srcAddress3Validout : OUT STD_LOGIC;
       desAddress0Validout, desAddress1Validout, desAddress2Validout, desAddress3Validout : OUT STD_LOGIC;
       packetType0, packetType1, packetType2, packetType3 : OUT STD_LOGIC;
--       srcAddress0out, srcAddress1out, srcAddress2out, srcAddress3out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--       desAddress0out, desAddress1out, desAddress2out, desAddress3out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       sendingsrcAddress0out, sendingdesAddress0out, sendingsrcAddress1out, sendingdesAddress1out, sendingsrcAddress2out, sendingdesAddress2out, sendingsrcAddress3out, sendingdesAddress3out : OUT STD_LOGIC;
       packet_size_comparator_out0, packet_size_comparator_out1, packet_size_comparator_out2, packet_size_comparator_out3 : OUT STD_LOGIC;     
	   portChoiceout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	   portReadyout  : OUT STD_LOGIC;
	   OMX_to_ARB_Done_out : OUT STD_LOGIC;
       TBL_to_FWD_ACK : IN STD_LOGIC;
	   TBL_to_FWD_Valid : IN STD_LOGIC;
	   TBL_to_FWD_Port : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	   FWD_to_XMT0_ACK, FWD_to_XMT1_ACK, FWD_to_XMT2_ACK, FWD_to_XMT3_ACK : OUT STD_LOGIC;
	   XMT0_to_FWD_spaceavailable, XMT1_to_FWD_spaceavailable, XMT2_to_FWD_spaceavailable,XMT3_to_FWD_spaceavailable : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
       FWD_to_TBL_desAddress, FWD_to_TBL_srcAddress : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
       FWD_to_TBL_srcPort : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
       FWD_to_TBL_ACK :OUT STD_LOGIC;
	   FWD_to_XMT0_DONE, FWD_to_XMT1_DONE, FWD_to_XMT2_DONE, FWD_to_XMT3_DONE : OUT STD_LOGIC;
	   FWD_to_XMT0_LENGTH, FWD_to_XMT1_LENGTH, FWD_to_XMT2_LENGTH, FWD_to_XMT3_LENGTH : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
	   FWD_to_XMT0_DATA, FWD_to_XMT1_DATA, FWD_to_XMT2_DATA, FWD_to_XMT3_DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

       
       );
       
END COMPONENT Test_Forwarding_Engine;

component xmt_emulator is
    port (clock               			: in  std_logic;
          reset               			: in  std_logic;
          XMT_to_FWD_spaceavailable		: out std_logic_vector(10 downto 0);
		  XMT_to_FWD_ACK				: out std_logic;
	      FWD_to_XMT_DATA				: in  std_logic_vector(7 downto 0);
	      FWD_to_XMT_ACK				: in  std_logic;
	      FWD_to_XMT_DONE				: in  std_logic;
	      FWD_to_XMT_LENGTH				: in  std_logic_vector(11 downto 0)
    );
end component;

component table_emulator is
    port (clock               			: in  std_logic;
          reset               			: in  std_logic;
          TBL_to_FWD_ACK				: out std_logic;
	      TBL_to_FWD_Valid				: out std_logic;
	      TBL_to_FWD_Port				: out std_logic_vector(2 downto 0);
	      FWD_to_TBL_ACK				: in  std_logic;
	      FWD_to_TBL_desAddress			: in  std_logic_vector(47 downto 0);
	      FWD_to_TBL_srcPort			: in  std_logic_vector(1 downto 0);
	      FWD_to_TBL_srcAddress			: in  std_logic_vector(47 downto 0)
	   );
end component;

component rcv_emulator is
    port (clock               			: in  std_logic;
          reset               			: in  std_logic;
          seed                          : in  std_logic_vector(7 downto 0);
          num_frames                    : in  std_logic_vector(10 downto 0);
          frame_count                   : out std_logic_vector(10 downto 0);
          RCV_to_FWD_DATA				: out std_logic_vector(7 downto 0);
		  RCV_to_FWD_LENGTH				: out std_logic_vector(11 downto 0);
		  RCV_to_FWD_FRAMEAVAILABLE		: out std_logic;
		  FWD_to_RCV_LENGTH_ACK			: in  std_logic;
		  FWD_to_RCV_FRAME_ACK			: in  std_logic;
		  rand_length                   : in  std_logic
	   );
end component;

component data_check is
    port (clock,reset         : in  std_logic;
          data                : in  std_logic_vector(7 downto 0);
          ack                 : in  std_logic;
          frame_len           : in  std_logic_vector(10 downto 0);
          port_num            : in  std_logic_vector(1 downto 0);
          data_err            : out std_logic;
          port_err            : out std_logic;
          len_err             : out std_logic;
          len_out             : out std_logic_vector(10 downto 0);
          frame_count         : out std_logic_vector(10 downto 0)
    );
end component;

component fwd_test_add11 is
	port
	(
		dataa		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
	);
end component;

component fwd_test_comp_11 is
	port
	(
		dataa		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
		AeB		: OUT STD_LOGIC 
	);
end component;

component fwd_test_ff1 is
	port
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC 
	);
end component;

begin

out_clock <= clock;

xmt0: xmt_emulator port map(clock,reset,XMT0_to_FWD_spaceavailable,XMT0_to_FWD_ACK,FWD_to_XMT0_DATA,FWD_to_XMT0_ACK,FWD_to_XMT0_DONE,FWD_to_XMT0_LENGTH);
xmt1: xmt_emulator port map(clock,reset,XMT1_to_FWD_spaceavailable,XMT1_to_FWD_ACK,FWD_to_XMT1_DATA,FWD_to_XMT1_ACK,FWD_to_XMT1_DONE,FWD_to_XMT1_LENGTH);
xmt2: xmt_emulator port map(clock,reset,XMT2_to_FWD_spaceavailable,XMT2_to_FWD_ACK,FWD_to_XMT2_DATA,FWD_to_XMT2_ACK,FWD_to_XMT2_DONE,FWD_to_XMT2_LENGTH);
xmt3: xmt_emulator port map(clock,reset,XMT3_to_FWD_spaceavailable,XMT3_to_FWD_ACK,FWD_to_XMT3_DATA,FWD_to_XMT3_ACK,FWD_to_XMT3_DONE,FWD_to_XMT3_LENGTH);

tbl: table_emulator port map(clock,reset,TBL_to_FWD_ACK,TBL_to_FWD_Valid,TBL_to_FWD_Port,FWD_to_TBL_ACK,FWD_to_TBL_desAddress,FWD_to_TBL_srcPort,FWD_to_TBL_srcAddress);

rcv0: rcv_emulator port map(clock,reset,"00000000" or seed,"00000000000" or num_frames,frame_count0,RCV0_to_FWD_DATA,RCV0_to_FWD_LENGTH,RCV0_to_FWD_FRAMEAVAILABLE,FWD_to_RCV0_LENGTH_ACK,FWD_to_RCV0_FRAME_ACK,random_lengths);
rcv1: rcv_emulator port map(clock,reset,"01000000" or seed,"00000000000" or num_frames,frame_count1,RCV1_to_FWD_DATA,RCV1_to_FWD_LENGTH,RCV1_to_FWD_FRAMEAVAILABLE,FWD_to_RCV1_LENGTH_ACK,FWD_to_RCV1_FRAME_ACK,random_lengths);
rcv2: rcv_emulator port map(clock,reset,"10000000" or seed,"00000000000" or num_frames,frame_count2,RCV2_to_FWD_DATA,RCV2_to_FWD_LENGTH,RCV2_to_FWD_FRAMEAVAILABLE,FWD_to_RCV2_LENGTH_ACK,FWD_to_RCV2_FRAME_ACK,random_lengths);
rcv3: rcv_emulator port map(clock,reset,"11000000" or seed,"00000000000" or num_frames,frame_count3,RCV3_to_FWD_DATA,RCV3_to_FWD_LENGTH,RCV3_to_FWD_FRAMEAVAILABLE,FWD_to_RCV3_LENGTH_ACK,FWD_to_RCV3_FRAME_ACK,random_lengths);


check0: data_check port map(clock,reset,FWD_to_XMT0_DATA,FWD_to_XMT0_ACK,FWD_to_XMT0_LENGTH(10 downto 0),"00",data_err0,port_err0,len_err0,len_out0,frame_out_count0);
check1: data_check port map(clock,reset,FWD_to_XMT1_DATA,FWD_to_XMT1_ACK,FWD_to_XMT1_LENGTH(10 downto 0),"01",data_err1,port_err1,len_err1,len_out1,frame_out_count1);
check2: data_check port map(clock,reset,FWD_to_XMT2_DATA,FWD_to_XMT2_ACK,FWD_to_XMT2_LENGTH(10 downto 0),"10",data_err2,port_err2,len_err2,len_out2,frame_out_count2);
check3: data_check port map(clock,reset,FWD_to_XMT3_DATA,FWD_to_XMT3_ACK,FWD_to_XMT3_LENGTH(10 downto 0),"11",data_err3,port_err3,len_err3,len_out3,frame_out_count3);

add1: fwd_test_add11 port map(frame_count0, frame_count1, frame_count01);
add2: fwd_test_add11 port map(frame_count2, frame_count3, frame_count23);
add3: fwd_test_add11 port map(frame_count01, frame_count23, frame_count);

add4: fwd_test_add11 port map(frame_out_count0, frame_out_count1, frame_out_count01);
add5: fwd_test_add11 port map(frame_out_count2, frame_out_count3, frame_out_count23);
add6: fwd_test_add11 port map(frame_out_count01, frame_out_count23, frame_out_count);

comp: fwd_test_comp_11 port map(frame_count,frame_out_count,all_frames_through);

ff1: fwd_test_ff1 port map(reset,clock,port_err_int or port_ever,port_ever);
ff2: fwd_test_ff1 port map(reset,clock,data_err_int or data_ever,data_ever);
ff3: fwd_test_ff1 port map(reset,clock,len_err_int or len_ever,len_ever);

fwd: Test_Forwarding_Engine port map(reset, clock, 
       RCV0_to_FWD_FRAMEAVAILABLE, RCV1_to_FWD_FRAMEAVAILABLE, RCV2_to_FWD_FRAMEAVAILABLE, RCV3_to_FWD_FRAMEAVAILABLE,
	   pass_data_out0, pass_data_out1, pass_data_out2, pass_data_out3,
	   RCV0_to_FWD_DATA, RCV1_to_FWD_DATA, RCV2_to_FWD_DATA, RCV3_to_FWD_DATA,
	   RCV0_to_FWD_LENGTH, RCV1_to_FWD_LENGTH, RCV2_to_FWD_LENGTH, RCV3_to_FWD_LENGTH,
	   FWD_to_RCV0_LENGTH_ACK, FWD_to_RCV1_LENGTH_ACK, FWD_to_RCV2_LENGTH_ACK, FWD_to_RCV3_LENGTH_ACK,
	   FWD_to_RCV0_FRAME_ACK, FWD_to_RCV1_FRAME_ACK, FWD_to_RCV2_FRAME_ACK, FWD_to_RCV3_FRAME_ACK,
	   count_out0, count_out1, count_out2, count_out3,
	   srcAddress0Validout, srcAddress1Validout, srcAddress2Validout, srcAddress3Validout,
	   desAddress0Validout, desAddress1Validout, desAddress2Validout, desAddress3Validout,
	   packetType0, packetType1, packetType2, packetType3,
	   sendingsrcAddress0out, sendingdesAddress0out, sendingsrcAddress1out, sendingdesAddress1out, sendingsrcAddress2out, sendingdesAddress2out, sendingsrcAddress3out, sendingdesAddress3out,
	   packet_size_comparator_out0, packet_size_comparator_out1, packet_size_comparator_out2, packet_size_comparator_out3,
	   portChoice, portReadyout , OMX_to_ARB_Done,
	   TBL_to_FWD_ACK, TBL_to_FWD_Valid, TBL_to_FWD_Port, 
	   FWD_to_XMT0_ACK, FWD_to_XMT1_ACK, FWD_to_XMT2_ACK, FWD_to_XMT3_ACK,
	   XMT0_to_FWD_spaceavailable, XMT1_to_FWD_spaceavailable, XMT2_to_FWD_spaceavailable, XMT3_to_FWD_spaceavailable,
	   FWD_to_TBL_desAddress, FWD_to_TBL_srcAddress, FWD_to_TBL_srcPort, FWD_to_TBL_ACK,
       FWD_to_XMT0_DONE, FWD_to_XMT1_DONE, FWD_to_XMT2_DONE, FWD_to_XMT3_DONE, 
       FWD_to_XMT0_LENGTH, FWD_to_XMT1_LENGTH, FWD_to_XMT2_LENGTH, FWD_to_XMT3_LENGTH, 
       FWD_to_XMT0_DATA, FWD_to_XMT1_DATA, FWD_to_XMT2_DATA, FWD_to_XMT3_DATA
       );
	   
--RCV1_to_FWD_DATA <= (7 downto 0 => '0'); -- q(28 downto 21);
--RCV1_to_FWD_LENGTH <= (11 downto 0 => '0'); -- q(40 downto 29);
--RCV1_to_FWD_FRAMEAVAILABLE <= '0'; --q(41);

--RCV2_to_FWD_DATA <= (7 downto 0 => '0'); --q(49 downto 42);
--RCV2_to_FWD_LENGTH <= (11 downto 0 => '0'); --q(61 downto 50);
--RCV2_to_FWD_FRAMEAVAILABLE <= '0'; --q(62);

--RCV3_to_FWD_DATA <= (7 downto 0 => '0'); --q(70 downto 63);
--RCV3_to_FWD_LENGTH <= (11 downto 0 => '0'); --q(82 downto 71);
--RCV3_to_FWD_FRAMEAVAILABLE <= '0'; --q(83);

testsrcAddress0Validout <= srcAddress0Validout;
testsrcAddress1Validout <= srcAddress1Validout;
testsrcAddress2Validout <= srcAddress2Validout;
testsrcAddress3Validout <= srcAddress3Validout;
testdesAddress0Validout <= desAddress0Validout;
testdesAddress1Validout <= desAddress1Validout;
testdesAddress2Validout <= desAddress2Validout;
testdesAddress3Validout <= desAddress3Validout;

FWD_to_RCV0_FRAME_ACK_out <= FWD_to_RCV0_FRAME_ACK;
FWD_to_RCV0_LENGTH_ACK_out <= FWD_to_RCV0_LENGTH_ACK;

FWD_to_RCV1_FRAME_ACK_out <= FWD_to_RCV1_FRAME_ACK;
FWD_to_RCV1_LENGTH_ACK_out <= FWD_to_RCV1_LENGTH_ACK;

FWD_to_RCV2_FRAME_ACK_out <= FWD_to_RCV2_FRAME_ACK;
FWD_to_RCV2_LENGTH_ACK_out <= FWD_to_RCV2_LENGTH_ACK;

FWD_to_RCV3_FRAME_ACK_out <= FWD_to_RCV3_FRAME_ACK;
FWD_to_RCV3_LENGTH_ACK_out <= FWD_to_RCV3_LENGTH_ACK;

FWD_to_TBL_ACK_out <= FWD_to_TBL_ACK;
FWD_to_TBL_desAddress_out <= FWD_to_TBL_desAddress;																		
FWD_to_TBL_srcPort_out <= FWD_to_TBL_srcPort;																
FWD_to_TBL_srcAddress_out <= FWD_to_TBL_srcAddress;																		
FWD_to_XMT0_DATA_out <= FWD_to_XMT0_DATA;
FWD_to_XMT1_DATA_out <= FWD_to_XMT1_DATA;
FWD_to_XMT2_DATA_out <= FWD_to_XMT2_DATA;
FWD_to_XMT3_DATA_out <= FWD_to_XMT3_DATA;						
FWD_to_XMT0_ACK_out <= FWD_to_XMT0_ACK;
FWD_to_XMT1_ACK_out <= FWD_to_XMT1_ACK;
FWD_to_XMT2_ACK_out <= FWD_to_XMT2_ACK;
FWD_to_XMT3_ACK_out <= FWD_to_XMT3_ACK;
FWD_to_XMT0_DONE_out <= FWD_to_XMT0_DONE;
FWD_to_XMT1_DONE_out <= FWD_to_XMT1_DONE;
FWD_to_XMT2_DONE_out <= FWD_to_XMT2_DONE;
FWD_to_XMT3_DONE_out <= FWD_to_XMT3_DONE;
FWD_to_XMT0_LENGTH_out <= FWD_to_XMT0_LENGTH;
FWD_to_XMT1_LENGTH_out <= FWD_to_XMT1_LENGTH;
FWD_to_XMT2_LENGTH_out <= FWD_to_XMT2_LENGTH;
FWD_to_XMT3_LENGTH_out <= FWD_to_XMT3_LENGTH;

RCV0_to_FWD_DATA_out <= RCV0_to_FWD_DATA;
RCV0_to_FWD_LENGTH_out <= RCV0_to_FWD_LENGTH;
RCV0_to_FWD_FRAMEAVAILABLE_out <= RCV0_to_FWD_FRAMEAVAILABLE;

RCV1_to_FWD_DATA_out <= RCV1_to_FWD_DATA;
RCV1_to_FWD_LENGTH_out <= RCV1_to_FWD_LENGTH;
RCV1_to_FWD_FRAMEAVAILABLE_out <= RCV1_to_FWD_FRAMEAVAILABLE;

RCV2_to_FWD_DATA_out <= RCV2_to_FWD_DATA;
RCV2_to_FWD_LENGTH_out <= RCV2_to_FWD_LENGTH;
RCV2_to_FWD_FRAMEAVAILABLE_out <= RCV2_to_FWD_FRAMEAVAILABLE;

RCV3_to_FWD_DATA_out <= RCV3_to_FWD_DATA;
RCV3_to_FWD_LENGTH_out <= RCV3_to_FWD_LENGTH;
RCV3_to_FWD_FRAMEAVAILABLE_out <= RCV3_to_FWD_FRAMEAVAILABLE;

TBL_to_FWD_ACK_out <= TBL_to_FWD_ACK;
TBL_to_FWD_Valid_out <= TBL_to_FWD_Valid;
TBL_to_FWD_Port_out	<= TBL_to_FWD_Port;

port_err_int <= port_err0 or port_err1 or port_err2 or port_err3;
data_err_int <= data_err0 or data_err1 or data_err2 or data_err3;
len_err_int <= len_err0 or len_err1 or len_err2 or len_err3;

port_err <= port_ever;
data_err <= data_ever;
len_err <= len_ever;

pass <= not (len_ever or port_ever or data_ever);

num_frames_through <= frame_out_count;

end behavior;